1. Field of the Invention
This invention relates generally to the cell structure, device configuration and fabrication process of power semiconductor devices. More particularly, this invention relates to a novel and improved cell structure, device configuration and improved process for fabricating a trenched semiconductor power device to achieve reduced source to drain resistance Rds, improved device ruggedness and breakdown voltage.
2. Description of the Related Art
As the cell density of the semiconductor power devices increases, there is a greater need to provide configuration such that the source to drain resistance Rsd can be reduced. Meanwhile, in order to provide power devices with broader spectrum of applications, the reduction of Rds, however must be achieved without comprising the device ruggedness and the breakdown voltage. The design and cell configurations to accomplish such requirements become more challenges to those of ordinary skill in the art, particularly when the cell density of the semiconductor power device is increased to a cell density that is above and beyond 600 M/in2 (six hundred million cells per square inch).
In U.S. Pat. No. 6,462,376 a three-mask process is disclosed to manufacture a DMOS device that has a stripe cell configuration with floating trench ring as termination. FIG. 1 shows a top view and a top view of the device as that disclosed in this patent. The configuration as disclosed however has the disadvantages due to the fact that the stripe cells have higher drain to source resistance (Rds) than the closed cells. Furthermore, the three-mask process allows a n+ region to locate in the termination area and the trench gate area and such configuration degrades the device ruggedness due the fact of additional latch-up of doped zones to become the parasitic N+PN bipolar transistors. When the device turns on, the active cells near the trench gates will be turned on first that can easily trigger the parasitic N+PN to cause potential damages to the device. The corners of the cells are particular vulnerable to such inadvertent triggering-on of the parasitic N+PN transistors due to the higher electrical field around the corner regions of the cells. For this reason, normally a source mask is employed to create a dummy cell that has no N+ region in the cell near the trench gate the device corners. Such techniques are required due the damages found near the device corners during a voltage surge with unclamped inductance switching (UIS) when a device is provided with such dummy cells as damage preventive structures. The disclosures made in this patent have further disadvantages arising from the process flow with the formation of the n+ and P-body before the trench gate formation. A punch-through problem is not preventable for a device with cell density that is higher than 112 million cells per square inch, i.e., as the device pitch is reduced to 2.4 um. The punch through issue arises due to the boron segregation during sacrificial oxidation and gate oxidation. The segregated boron near channel region leads reduction in doping concentration thus increases the likelihood of punch through at the channel region under the condition of reverse bias between drain and source.
Therefore, there is still a need in the art of the semiconductor device fabrication, particularly for trenched power MOSFET design and fabrication, to provide a novel cell structure, device configuration and fabrication process that would resolve these difficulties and design limitations. Specifically, it is desirable to maintain low gate resistance and in the meanwhile, it is further desirable to overcome the problems above discussed difficulties such that further increase of cell density of a trenched semiconductor power device can be achieved.